Introduction

With the rapid growth of electric vehicles, photovoltaic energy storage systems, industrial power supplies, and high-frequency/high-voltage electronic devices, 4H-SiC (4H Silicon Carbide) wafers have become one of the most critical foundational materials in the third-generation semiconductor industry.
However, 4H-SiC possesses extremely high hardness, strong covalent bonding, and outstanding chemical stability, making wafer processing significantly more difficult than conventional silicon materials. Among all manufacturing processes, Chemical Mechanical Polishing (CMP) is the core technology for achieving ultra-high-quality SiC wafer surfaces and is also one of the most complex and expensive processes in SiC wafer fabrication.
This article systematically introduces the development status, working principles, key process parameters, and current challenges of CMP technology for 4H-SiC wafers.
 

1. Background of CMP Technology

CMP technology first emerged in the mid-20th century and was initially used for the planarization of glass and metal surfaces.
In 1988, IBM first introduced CMP into integrated circuit manufacturing. Since then, CMP has gradually become a core process in semiconductor wafer fabrication. The greatest advantage of CMP is its ability to simultaneously achieve:

•    •  Global planarization
•    •  Local planarization

As a result, CMP has been widely applied in silicon wafers, compound semiconductors, and advanced packaging technologies.
In 1997, CMP was first applied to the planarization of SiC wafers, marking the beginning of ultra-precision polishing technology for 4H-SiC wafers.

 

Figure 1. Typical Manufacturing Process of 4H-SiC Wafers

The figure illustrates the complete manufacturing process of 4H-SiC wafers from crystal boule slicing to final CMP polishing, including:

•    •  Wire Sawing
•    •  Edge Rounding
•    •  Grinding
•    •  Lapping
•    •  Chemical Mechanical Polishing (CMP)

This diagram helps readers understand the overall wafer fabrication workflow before entering the detailed CMP process discussion.
 

2. Composition and Working Principle of the 4H-SiC CMP System

A typical CMP system mainly consists of the following components:

•    •  Polishing slurry
•    •  Polishing pad
•    •  Polishing machine
•    •  Polishing head
•    •  Polishing plate

During the CMP process, the 4H-SiC wafer is fixed to the bottom of the polishing head.
The polishing slurry is continuously supplied onto the polishing pad surface. Under a certain pressure, the wafer, slurry, and polishing pad remain in close contact while rotating relative to each other, enabling material removal through combined chemical and mechanical interactions.
The fundamental principle of CMP can be summarized as:

“Chemical Oxidation + Mechanical Removal”

The detailed process includes:
1. Oxidants in the slurry chemically oxidize the SiC surface;
2. A relatively soft oxide layer forms on the wafer surface;
3. Abrasive particles in the slurry mechanically remove the oxide layer;
4. The newly exposed surface is oxidized again;
5. Mechanical removal continues repeatedly.
Through the continuous cycle of oxidation and removal, ultra-precision planarization of the wafer surface is ultimately achieved.

Figure 2. Schematic Diagram of a Typical CMP System

This figure shows the main components of a CMP system, including:

•    •  Polishing head
•    •  Polishing plate
•    •  Polishing pad
•    •  Polishing slurry
•    •  4H-SiC wafer

The diagram illustrates how the wafer, slurry, and polishing pad interact under pressure and rotational motion during the CMP process.
 

3. Characteristics of 4H-SiC CMP Processing

3.1 Extremely Low Material Removal Rate (MRR)

Due to the exceptional hardness of SiC, early CMP processes exhibited very low polishing efficiency.
Studies have shown:

•    •  Mechanical polishing MRR: approximately 2–2.25 μm/h
•    •  CMP MRR: typically below 200 nm/h

Compared with conventional silicon wafer polishing, the CMP efficiency of SiC is significantly lower.
Currently, CMP processing of either the Si-face or C-face of a 4H-SiC wafer usually requires 3–5 hours.
CMP alone accounts for approximately 30%–40% of the total SiC wafer processing cost.
 

3.2 Atomic-Level Surface Quality

Although the material removal efficiency is relatively low, CMP can achieve atomic-level surface quality.
Research has shown that when the surface roughness of a 4H-SiC wafer reaches below:
Ra < 0.06\ \mathrm{nm}
a typical atomic step-terrace structure appears on the wafer surface.
AFM (Atomic Force Microscopy) measurements indicate that the atomic step height is approximately:
h \approx 0.25\ \mathrm{nm}
This value closely matches the theoretical lattice height of a 4H-SiC bilayer, demonstrating that CMP technology is capable of producing truly atomically smooth surfaces.

Figure 3. Atomic Step-Terrace Structure on the Surface of 4H-SiC Wafers

(a) AFM image showing the atomic step structure on the wafer surface;
(b) Measured atomic step dimensions from X1 to X2;
(c) Formation mechanism of the atomic step structure on the 4H-SiC surface, where d and h represent the width and height of the atomic steps, respectively.
 

4. Material Removal Mechanism of CMP

The essence of 4H-SiC CMP is a dynamic cyclic process involving:

“Oxide Layer Formation + Oxide Layer Removal”

First, oxidants in the polishing slurry chemically oxidize the SiC surface, forming a relatively soft Si-C-O transition oxide layer.
Then, abrasive particles together with the polishing pad mechanically remove the oxide layer.
Since the oxide layer is softer than the SiC substrate, it can be effectively removed through mechanical action.
By continuously repeating:

•    •  Oxidation
•    •  Mechanical stripping
•    •  Re-oxidation

the wafer surface is gradually planarized layer by layer.
Researchers generally believe that:

“The oxidation reaction is the rate-limiting step in the CMP process.”

Therefore, improving oxidation efficiency has become a major direction for enhancing CMP performance.

Figure 4. Material Removal Mechanism of the 4H-SiC CMP Process

This figure illustrates the dynamic process of oxide layer formation and removal during CMP, including:
1. Surface oxidation of SiC
2. Oxide layer formation
3. Mechanical removal by abrasive particles
4. Continuous cyclic polishing
Different colors may be used to distinguish:

•    •  4H-SiC wafer
•    •  Polishing slurry
•    •  Abrasive particles
•    •  Polishing pad
•    •  Oxide layer

5. Oxidants and CMP Efficiency Optimization

Because SiC exhibits extremely strong chemical stability, researchers have continuously explored methods to enhance oxidation efficiency.
Early CMP systems commonly used:

•    •  H₂O₂ as the oxidant
•    •  Colloidal SiO₂ as the abrasive

However, the MRR still remained below:
200\ \mathrm{nm/h}
Later, potassium permanganate (KMnO₄) attracted considerable attention due to its strong oxidation capability.
Using KMnO₄:

•    •  MRR reached approximately 185 nm/h
•    •  Surface roughness Ra was about 0.254 nm

Under strongly acidic conditions, the MRR could further increase to:
MRR \approx 308\ \mathrm{nm/h}
However, simply increasing oxidation strength is not sufficient.
If the mechanical removal capability is inadequate, the oxide layer cannot be removed efficiently, limiting the overall CMP performance.
Therefore, the key to CMP optimization lies in balancing:

•    •  Chemical oxidation
•    •  Mechanical removal

6. Current Challenges of 4H-SiC CMP

Despite significant progress, several major challenges still exist in 4H-SiC CMP processing.

Low Processing Efficiency

Ultra-low MRR limits manufacturing throughput.

High Manufacturing Cost

CMP remains one of the most expensive steps in SiC wafer fabrication.

Larger Wafer Sizes

The transition toward 6-inch and 8-inch wafers requires much higher flatness and uniformity.

Difficult Defect Control

Scratches, subsurface damage, and residual defects continue to affect device yield.

Environmental Concerns

Traditional polishing slurry systems may create wastewater treatment and environmental issues.
 

7. Future Development Trends

Future development directions for 4H-SiC CMP include:

•    •  High-efficiency low-damage CMP
•    •  Novel oxidant systems
•    •  Nano-abrasive technologies
•    •  Fixed abrasive CMP
•    •  Electrochemical-assisted CMP
•    •  Plasma-assisted CMP
•    •  AI-based intelligent process control
•    •  Uniform processing for ultra-large wafers

As the markets for electric vehicles and high-voltage power devices continue to expand, high-efficiency, low-cost, and high-quality CMP technology will become a critical competitive factor in the SiC industry.
 

Conclusion

CMP is one of the most critical and complex processes in 4H-SiC wafer manufacturing.
Although current technology can already achieve atomically smooth surfaces, low material removal rates, high processing costs, and complicated chemical-mechanical interactions remain major barriers to large-scale industrialization.
In the future, advancements in polishing slurry chemistry, intelligent processing equipment, and novel assisted CMP technologies are expected to further improve the efficiency and surface quality of 4H-SiC wafer processing, providing stronger support for the continued development of the third-generation semiconductor industry.

Related products:
4H-SiC Wafers
6-inch SiC Wafers
8-inch SiC Wafers